Modern integrated circuits are typically constructed in a thin layer in a semiconducting layer on a substrate wafer such as silicon. This essentially two-dimensional structure limits both the size of the integrated circuit and the speed at which the circuit operates. The distance between the farthest separated components that must communicate with one another on the chip determines the speed at which an integrated circuit operates. For any given number of components, the path lengths will, in general, be significantly reduced if the circuit can be laid out as a three-dimensional structure consisting of a number of vertically-stacked layers of circuitry, provided the vertical distances between the layers are much smaller than the width of the chips that make up the individual layers.
The circuitry that can be economically constructed on any type of wafer is also limited. For example, the fabrication processes utilized for constructing CCD optical sensors do not lend themselves to constructing CMOS logic circuits. Hence, an optical sensor having a CCD array and the corresponding logic circuits must be broken into two substrates that are connected electrically after the circuit elements on each substrate have been fabricated. Prior art versions of such hybrid circuits are limited in the number of inter-substrate connections that can be utilized.
One promising scheme for providing stacked structures utilizes a method for stacking and bonding entire wafers. In this method, integrated circuits are fabricated on conventional wafers. The circuitry on the front surface of each wafer is covered with an insulating layer having metallic pads that make contact with the underlying circuitry and act as electrical connection points between the two wafers. The front surfaces of the wafers are then placed in contact with one another and bonded via thermal compression bonding. If more than two wafers are to be connected, one of the wafers is then thinned to a thickness of a few microns by etching or mechanically grinding the back surface of that wafer. Once the wafer has been thinned, a new set of pads is constructed on the backside of the thinned wafer. Some of these backside pads are connected to the circuitry on the front side of the wafer through metal-filled vias that connect the front and backsides of the thinned wafer. These backside pads provide the connection points for adding yet another wafer to the stack. The process is then repeated until the desired number of layers has been bonded to form the three-dimensional stack. The three-dimensional stack is then cut into three-dimensional chips and packaged.
In conventional wafer processing schemes, the front side of each wafer includes fiducial marks that are utilized in positioning the exposure projecting apparatus used in the various lithographic processing steps. The front sides of the wafers used in the stacking process described above include such fiducial marks. However, when the wafer is bonded by its front side to the stack of wafers and then thinned, there are no fiducial marks on the backside of the wafer. Hence, positioning the lithographic projector during the steps needed for the construction of the new set of pads on the backside of the wafer has problems. The current technology that is available for lithographic projection on the backside of stacked wafers results in a large misalignment (˜5 um). In principle, the fiducial marks on the front side of the wafer can be utilized if the wafer is thinned sufficiently, allowing white-light alignment utilizing fiducial marks which are placed on the front side and become visible from the back side after thinning the wafer.
Alternatively the wafer is also reasonably transparent in the long wavelength portion of the spectrum. However, such long wavelength imaging provides only limited positioning accuracy.